----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:50:02 04/19/2010 
-- Design Name: 
-- Module Name:    ad8020_interface - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ad8020_interface is
    Port ( DB : in  STD_LOGIC_VECTOR (7 downto 0);
           INT : in  STD_LOGIC;
           WR : out  STD_LOGIC;
           clk_i : in  STD_LOGIC;
           start_i : in  STD_LOGIC;
           adr_o : out  STD_LOGIC_VECTOR (11 downto 0);
           data_o : out  STD_LOGIC_VECTOR (31 downto 0);
           ena_o : out  STD_LOGIC;
           we_o : out  STD_LOGIC;
           clk_o : out  STD_LOGIC;
			  int_out : out STD_LOGIC;
			  state_o : out  STD_LOGIC_VECTOR (2 downto 0));
end ad8020_interface;

architecture Behavioral of ad8020_interface is

signal state : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal data : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal adr_counter : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";


begin
P1: process(clk_i)

begin

if rising_edge(clk_i) then

	if start_i = '1' then 
	
	   if state = "000" then
		WR <= '0';
		state <= "001";
		
		elsif state = "001" then
		WR <= '1';
		state <= "010";
		
		elsif state = "010" then
		if INT = '0' then
			state <= "011";
		end if;
		
	
		elsif state = "011" then 
			 adr_o <= adr_counter;
			 data_o(7 downto 0) <= DB;
			 we_o <= '1';
			 ena_o <= '1';
			 state <= "100";
		 elsif state = "100" then
			 adr_counter <= adr_counter + "1";
			 ena_o <= '0';
			 if adr_counter = "111110111000" then 
				 state <= "110";
				 int_out <= '1';
			 else state <= "000";
			 end if;
		end if;

	else 
		adr_counter <= "000000011000";
		state <= "000";
		int_out <= '0';
		WR <= '1';
	end if;
end if;

--if rising_edge(clk_i) and start_i = '1' then
--
-- if state = "000" then 
-- --adr_o <= adr_counter;
-- data_o(7 downto 0) <= "11111111";
-- we_o <= '1';
-- ena_o <= '1';
-- state := "001";
--	
--
-- elsif state = "001" then 
----	adr_counter := adr_counter + "1";
--	ena_o <= '0';
--	
----		if adr_counter = "011111010000" then 
----		state := "010";
----		int_out <= '1';
----		else state := "000";
----		end if;
--end if;
-- 
--elsif start_i = '0' then
--	--adr_counter := "000001011111";
--	state := "000";
--	int_out <= '0';
--end if;




--if(rising_edge(clk_i)) then
-- if start_i = '0' and not(state = "110")  then 
--	state := "000";
--	WR <= '1';
--	ena_o <= '1';
--	
-- elsif state = "000" then 
-- 
-- ena_o <= '0';
-- WR <= '1';
-- if start_i = '1' then state := "001";
-- end if;
-- 
-- elsif state = "001" then 
--	WR <= '0';
--	ena_o <= '0';
--	state := "010";
-- 
-- 
-- elsif state = "010" then
--  if INT = '1' then 
--		state := "011";
--		WR <= '1';
--  end if;
--  
-- elsif state = "011" then
-- if INT = '0' then 
-- data := DB;
-- state := "100";
-- adr_counter := adr_counter + 1;
-- WR <= '0';
-- end if;
-- 
-- elsif state = "100" then
-- adr_o <= adr_counter;
-- data_o(7 downto 0) <= "11111111";
-- we_o <= '1';
-- ena_o <= '1';
-- state := "101";
-- WR <= '1';
-- 
-- elsif state = "101" then
-- ena_o <= '0';
-- if adr_counter = "0100000110000" then
-- state := "110";
-- int_out <= '1';
-- else state := "001";
-- end if;
-- 
-- elsif state = "110" then
--	int_out <= '1';
--	 if start_i = '0' then state := "000";
--	 end if;
-- 
-- end if;
--end if;
--state_o <= state;
end process;
end Behavioral;

